1. 28 Aug, 2013 1 commit
  2. 18 Jul, 2013 1 commit
  3. 26 May, 2013 1 commit
  4. 04 May, 2013 1 commit
  5. 11 Feb, 2013 1 commit
  6. 22 Jan, 2013 4 commits
  7. 16 Jan, 2013 1 commit
  8. 07 Dec, 2012 3 commits
  9. 26 Nov, 2012 1 commit
  10. 11 Oct, 2012 1 commit
  11. 03 Oct, 2012 1 commit
  12. 02 Oct, 2012 3 commits
  13. 21 Sep, 2012 2 commits
  14. 20 Sep, 2012 1 commit
  15. 15 Sep, 2012 1 commit
  16. 13 Aug, 2012 2 commits
  17. 10 Aug, 2012 1 commit
  18. 07 Aug, 2012 1 commit
  19. 01 Jul, 2012 1 commit
  20. 22 Jun, 2012 1 commit
  21. 18 Jun, 2012 1 commit
  22. 08 Jun, 2012 3 commits
  23. 07 May, 2012 1 commit
  24. 03 May, 2012 1 commit
  25. 02 May, 2012 2 commits
    • Mans Rullgard's avatar
      arm: intreadwrite: disable inline asm for gcc 4.7 and later · ababec7b
      Mans Rullgard authored
      Starting with version 4.7, gcc properly supports unaligned
      memory accesses on ARM.  Not using the inline asm with these
      compilers results in better code.
      Signed-off-by: 's avatarMans Rullgard <mans@mansr.com>
      ababec7b
    • Mans Rullgard's avatar
      arm: intreadwrite: fix inline asm constraints for gcc 4.6 and later · adebad07
      Mans Rullgard authored
      With a dereferenced type-cast pointer as memory operand, gcc 4.6
      and later will sometimes copy the data to a temporary location,
      the address of which is used as the operand value, if it thinks
      the target address might be misaligned.  Using a pointer to a
      packed struct type instead does the right thing.
      
      The 16-bit case is special since the ldrh instruction addressing
      modes are limited compared to ldr.  The "Uq" constraint produces a
      memory reference suitable for an ldrsb instruction, which supports
      the same addressing modes as ldrh.  However, the restrictions appear
      to apply only when the operand addresses a single byte.  The memory
      reference must thus be split into two operands each targeting one
      byte.  Finally, the "Uq" constraint is only available in ARM mode.
      The Thumb-2 ldrh instruction supports most addressing modes so the
      normal "m" constraint can be used there.
      Signed-off-by: 's avatarMans Rullgard <mans@mansr.com>
      adebad07
  26. 22 Apr, 2012 1 commit
  27. 12 Mar, 2012 1 commit
    • Janne Grunau's avatar
      remove iwmmxt optimizations · 363bd1c6
      Janne Grunau authored
      The were broken since August of 2010 without anyone noticing until
      three weeks ago. Nobody cares about it anymore and hopefully Marvell
      will support NEON like in the PXA978 from now on.
      363bd1c6
  28. 12 Dec, 2011 1 commit