x86.h 9.29 KB
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/*
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 *  Copyright (c) 2010 The WebM project authors. All Rights Reserved.
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 *
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 *  Use of this source code is governed by a BSD-style license
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 *  that can be found in the LICENSE file in the root of the source
 *  tree. An additional intellectual property rights grant can be found
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 *  in the file PATENTS.  All contributing project authors may
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 *  be found in the AUTHORS file in the root of the source tree.
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 */

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#ifndef VPX_PORTS_X86_H_
#define VPX_PORTS_X86_H_
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#include <stdlib.h>
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#if defined(_MSC_VER)
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#include <intrin.h> /* For __cpuidex, __rdtsc */
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#endif

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#include "vpx_config.h"
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#include "vpx/vpx_integer.h"
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#ifdef __cplusplus
extern "C" {
#endif

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typedef enum {
  VPX_CPU_UNKNOWN = -1,
  VPX_CPU_AMD,
  VPX_CPU_AMD_OLD,
  VPX_CPU_CENTAUR,
  VPX_CPU_CYRIX,
  VPX_CPU_INTEL,
  VPX_CPU_NEXGEN,
  VPX_CPU_NSC,
  VPX_CPU_RISE,
  VPX_CPU_SIS,
  VPX_CPU_TRANSMETA,
  VPX_CPU_TRANSMETA_OLD,
  VPX_CPU_UMC,
  VPX_CPU_VIA,

  VPX_CPU_LAST
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} vpx_cpu_t;
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#if defined(__GNUC__) && __GNUC__ || defined(__ANDROID__)
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#if ARCH_X86_64
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#define cpuid(func, func2, ax, bx, cx, dx)                      \
  __asm__ __volatile__("cpuid           \n\t"                   \
                       : "=a"(ax), "=b"(bx), "=c"(cx), "=d"(dx) \
                       : "a"(func), "c"(func2));
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#else
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#define cpuid(func, func2, ax, bx, cx, dx)     \
  __asm__ __volatile__(                        \
      "mov %%ebx, %%edi   \n\t"                \
      "cpuid              \n\t"                \
      "xchg %%edi, %%ebx  \n\t"                \
      : "=a"(ax), "=D"(bx), "=c"(cx), "=d"(dx) \
      : "a"(func), "c"(func2));
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#endif
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#elif defined(__SUNPRO_C) || \
    defined(__SUNPRO_CC) /* end __GNUC__ or __ANDROID__*/
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#if ARCH_X86_64
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#define cpuid(func, func2, ax, bx, cx, dx)     \
  asm volatile(                                \
      "xchg %rsi, %rbx \n\t"                   \
      "cpuid           \n\t"                   \
      "movl %ebx, %edi \n\t"                   \
      "xchg %rsi, %rbx \n\t"                   \
      : "=a"(ax), "=D"(bx), "=c"(cx), "=d"(dx) \
      : "a"(func), "c"(func2));
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#else
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#define cpuid(func, func2, ax, bx, cx, dx)     \
  asm volatile(                                \
      "pushl %ebx       \n\t"                  \
      "cpuid            \n\t"                  \
      "movl %ebx, %edi  \n\t"                  \
      "popl %ebx        \n\t"                  \
      : "=a"(ax), "=D"(bx), "=c"(cx), "=d"(dx) \
      : "a"(func), "c"(func2));
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#endif
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#else /* end __SUNPRO__ */
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#if ARCH_X86_64
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#if defined(_MSC_VER) && _MSC_VER > 1500
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#define cpuid(func, func2, a, b, c, d) \
  do {                                 \
    int regs[4];                       \
    __cpuidex(regs, func, func2);      \
    a = regs[0];                       \
    b = regs[1];                       \
    c = regs[2];                       \
    d = regs[3];                       \
  } while (0)
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#else
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#define cpuid(func, func2, a, b, c, d) \
  do {                                 \
    int regs[4];                       \
    __cpuid(regs, func);               \
    a = regs[0];                       \
    b = regs[1];                       \
    c = regs[2];                       \
    d = regs[3];                       \
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  } while (0)
#endif
#else
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#define cpuid(func, func2, a, b, c, d)                              \
  __asm mov eax, func __asm mov ecx, func2 __asm cpuid __asm mov a, \
      eax __asm mov b, ebx __asm mov c, ecx __asm mov d, edx
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#endif
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#endif /* end others */
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// NaCl has no support for xgetbv or the raw opcode.
#if !defined(__native_client__) && (defined(__i386__) || defined(__x86_64__))
static INLINE uint64_t xgetbv(void) {
  const uint32_t ecx = 0;
  uint32_t eax, edx;
  // Use the raw opcode for xgetbv for compatibility with older toolchains.
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  __asm__ volatile(".byte 0x0f, 0x01, 0xd0\n"
                   : "=a"(eax), "=d"(edx)
                   : "c"(ecx));
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  return ((uint64_t)edx << 32) | eax;
}
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#elif (defined(_M_X64) || defined(_M_IX86)) && defined(_MSC_FULL_VER) && \
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    _MSC_FULL_VER >= 160040219  // >= VS2010 SP1
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#include <immintrin.h>
#define xgetbv() _xgetbv(0)
#elif defined(_MSC_VER) && defined(_M_IX86)
static INLINE uint64_t xgetbv(void) {
  uint32_t eax_, edx_;
  __asm {
    xor ecx, ecx  // ecx = 0
    // Use the raw opcode for xgetbv for compatibility with older toolchains.
    __asm _emit 0x0f __asm _emit 0x01 __asm _emit 0xd0
    mov eax_, eax
    mov edx_, edx
  }
  return ((uint64_t)edx_ << 32) | eax_;
}
#else
#define xgetbv() 0U  // no AVX for older x64 or unrecognized toolchains.
#endif

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#if defined(_MSC_VER) && _MSC_VER >= 1700
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#undef NOMINMAX
#define NOMINMAX
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#ifndef WIN32_LEAN_AND_MEAN
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#define WIN32_LEAN_AND_MEAN
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#endif
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#include <windows.h>
#if WINAPI_FAMILY_PARTITION(WINAPI_FAMILY_APP)
#define getenv(x) NULL
#endif
#endif

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#define HAS_MMX 0x001
#define HAS_SSE 0x002
#define HAS_SSE2 0x004
#define HAS_SSE3 0x008
#define HAS_SSSE3 0x010
#define HAS_SSE4_1 0x020
#define HAS_AVX 0x040
#define HAS_AVX2 0x080
#define HAS_AVX512 0x100
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#ifndef BIT
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#define BIT(n) (1u << n)
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#endif

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static INLINE int x86_simd_caps(void) {
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  unsigned int flags = 0;
  unsigned int mask = ~0;
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  unsigned int max_cpuid_val, reg_eax, reg_ebx, reg_ecx, reg_edx;
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  char *env;
  (void)reg_ebx;
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  /* See if the CPU capabilities are being overridden by the environment */
  env = getenv("VPX_SIMD_CAPS");
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  if (env && *env) return (int)strtol(env, NULL, 0);
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  env = getenv("VPX_SIMD_CAPS_MASK");
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  if (env && *env) mask = (unsigned int)strtoul(env, NULL, 0);
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  /* Ensure that the CPUID instruction supports extended features */
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  cpuid(0, 0, max_cpuid_val, reg_ebx, reg_ecx, reg_edx);
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  if (max_cpuid_val < 1) return 0;
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  /* Get the standard feature flags */
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  cpuid(1, 0, reg_eax, reg_ebx, reg_ecx, reg_edx);
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  if (reg_edx & BIT(23)) flags |= HAS_MMX;
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  if (reg_edx & BIT(25)) flags |= HAS_SSE; /* aka xmm */
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  if (reg_edx & BIT(26)) flags |= HAS_SSE2; /* aka wmt */
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  if (reg_ecx & BIT(0)) flags |= HAS_SSE3;
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  if (reg_ecx & BIT(9)) flags |= HAS_SSSE3;
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  if (reg_ecx & BIT(19)) flags |= HAS_SSE4_1;
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  // bits 27 (OSXSAVE) & 28 (256-bit AVX)
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  if ((reg_ecx & (BIT(27) | BIT(28))) == (BIT(27) | BIT(28))) {
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    if ((xgetbv() & 0x6) == 0x6) {
      flags |= HAS_AVX;
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      if (max_cpuid_val >= 7) {
        /* Get the leaf 7 feature flags. Needed to check for AVX2 support */
        cpuid(7, 0, reg_eax, reg_ebx, reg_ecx, reg_edx);
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        if (reg_ebx & BIT(5)) flags |= HAS_AVX2;
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        // bits 16 (AVX-512F) & 17 (AVX-512DQ) & 28 (AVX-512CD) &
        // 30 (AVX-512BW) & 32 (AVX-512VL)
        if ((reg_ebx & (BIT(16) | BIT(17) | BIT(28) | BIT(30) | BIT(31))) ==
            (BIT(16) | BIT(17) | BIT(28) | BIT(30) | BIT(31)))
          flags |= HAS_AVX512;
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      }
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    }
  }
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  return flags & mask;
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}

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// Note:
//  32-bit CPU cycle counter is light-weighted for most function performance
//  measurement. For large function (CPU time > a couple of seconds), 64-bit
//  counter should be used.
// 32-bit CPU cycle counter
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static INLINE unsigned int x86_readtsc(void) {
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#if defined(__GNUC__) && __GNUC__
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  unsigned int tsc;
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  __asm__ __volatile__("rdtsc\n\t" : "=a"(tsc) :);
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  return tsc;
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#elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
  unsigned int tsc;
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  asm volatile("rdtsc\n\t" : "=a"(tsc) :);
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  return tsc;
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#else
#if ARCH_X86_64
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  return (unsigned int)__rdtsc();
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#else
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  __asm rdtsc;
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#endif
#endif
}
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// 64-bit CPU cycle counter
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static INLINE uint64_t x86_readtsc64(void) {
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#if defined(__GNUC__) && __GNUC__
  uint32_t hi, lo;
  __asm__ __volatile__("rdtsc" : "=a"(lo), "=d"(hi));
  return ((uint64_t)hi << 32) | lo;
#elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
  uint_t hi, lo;
  asm volatile("rdtsc\n\t" : "=a"(lo), "=d"(hi));
  return ((uint64_t)hi << 32) | lo;
#else
#if ARCH_X86_64
  return (uint64_t)__rdtsc();
#else
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  __asm rdtsc;
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#endif
#endif
}
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#if defined(__GNUC__) && __GNUC__
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#define x86_pause_hint() __asm__ __volatile__("pause \n\t")
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#elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
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#define x86_pause_hint() asm volatile("pause \n\t")
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#else
#if ARCH_X86_64
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#define x86_pause_hint() _mm_pause();
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#else
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#define x86_pause_hint() __asm pause
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#endif
#endif

#if defined(__GNUC__) && __GNUC__
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static void x87_set_control_word(unsigned short mode) {
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  __asm__ __volatile__("fldcw %0" : : "m"(*&mode));
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}
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static unsigned short x87_get_control_word(void) {
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  unsigned short mode;
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  __asm__ __volatile__("fstcw %0\n\t" : "=m"(*&mode) :);
  return mode;
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}
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#elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
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static void x87_set_control_word(unsigned short mode) {
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  asm volatile("fldcw %0" : : "m"(*&mode));
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}
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static unsigned short x87_get_control_word(void) {
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  unsigned short mode;
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  asm volatile("fstcw %0\n\t" : "=m"(*&mode) :);
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  return mode;
}
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#elif ARCH_X86_64
/* No fldcw intrinsics on Windows x64, punt to external asm */
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extern void vpx_winx64_fldcw(unsigned short mode);
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extern unsigned short vpx_winx64_fstcw(void);
#define x87_set_control_word vpx_winx64_fldcw
#define x87_get_control_word vpx_winx64_fstcw
#else
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static void x87_set_control_word(unsigned short mode) {
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  __asm { fldcw mode }
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}
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static unsigned short x87_get_control_word(void) {
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  unsigned short mode;
  __asm { fstcw mode }
  return mode;
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}
#endif

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static INLINE unsigned int x87_set_double_precision(void) {
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  unsigned int mode = x87_get_control_word();
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  x87_set_control_word((mode & ~0x300) | 0x200);
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  return mode;
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}

extern void vpx_reset_mmx_state(void);

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#ifdef __cplusplus
}  // extern "C"
#endif

#endif  // VPX_PORTS_X86_H_