1. 23 Dec, 2015 3 commits
  2. 19 Dec, 2015 1 commit
  3. 18 Dec, 2015 2 commits
  4. 17 Dec, 2015 1 commit
    • Jian Zhou's avatar
      Code clean of sad4xN(_avg)_sse · b158d9a6
      Jian Zhou authored
      Replace MMX with SSE2, reduce psadbw ops which may help Silvermont.
      
      Change-Id: Ic7aec15245c9e5b2f3903dc7631f38e60be7c93d
      b158d9a6
  5. 14 Dec, 2015 1 commit
  6. 11 Dec, 2015 1 commit
    • Jian Zhou's avatar
      Code clean of tm_predictor_32x32 · 88120481
      Jian Zhou authored
      Reallocate the xmm register usage so that no ARCH_X86_64 required.
      Reduce memory access to the left neighbor by half.
      Speed up by single digit on big core machine.
      
      Change-Id: I392515ed8e8aeb02e6a717b3966b1ba13f5be990
      88120481
  7. 10 Dec, 2015 1 commit
    • Jian Zhou's avatar
      SSE2 based h_predictor_32x32 · c90a8a1a
      Jian Zhou authored
      Relocate the function from SSSE3 to SSE2, Unroll loop from 16 to 8,
      and reduce mem access to left.
      Speed up by single digit in ./test_intra_pred_speed on big core
      machines.
      
      Change-Id: I2b7fc95ffc0c42145be2baca4dc77116dff1c960
      c90a8a1a
  8. 09 Dec, 2015 1 commit
  9. 08 Dec, 2015 1 commit
    • Jian Zhou's avatar
      Re-enable SSE2 based intra 4x4 prediction · aa5b517a
      Jian Zhou authored
      4x4 Intra predictor implemented with MMX is replaced with SSE2.
      Segfault in change 315561 when decoding vp8 is taken care of.
      
      Change-Id: I083a7cb4eb8982954c20865160f91ebec777ec76
      aa5b517a
  10. 05 Dec, 2015 3 commits
  11. 04 Dec, 2015 4 commits
    • Jian Zhou's avatar
      Speed up h_predictor_16x16 · e86c7c86
      Jian Zhou authored
      Relocate the function from SSSE3 to SSE2, Unroll loop from 8 to 4,
      and reduce mem access to left.
      Speed up by >20% in ./test_intra_pred_speed.
      
      Change-Id: Ie48229c2e32404706b722442942c84983bda74cc
      e86c7c86
    • Jian Zhou's avatar
      Speed up h_predictor_8x8 · da3f08fa
      Jian Zhou authored
      Relocate the function from SSSE3 to SSE2, Unroll loop from 4 to 2,
      and reduce mem access to left.
      Speed up by >20% in ./test_intra_pred_speed.
      
      Change-Id: Ib9f1846819783b6e05e2a310c930eb844b2b4d2e
      da3f08fa
    • Jian Zhou's avatar
      MMX in intra 8x8 prediction replaced with SSE2 · aa2764ab
      Jian Zhou authored
      8x8 Intra predictor implemented with MMX is replaced with SSE2.
      
      Change-Id: I0c90e7c1e1e6942489ac2bfe58903b728aac7a52
      aa2764ab
    • Jian Zhou's avatar
      MMX in intra 4x4 prediction replaced with SSE2 · 89a1efa4
      Jian Zhou authored
      4x4 Intra predictor implemented with MMX is replaced with SSE2.
      
      Change-Id: Id57da2a7c38832d0356bc998790fc1989d39eafc
      89a1efa4
  12. 30 Nov, 2015 1 commit
    • Jian Zhou's avatar
      SSE2 speed up of h_predictor_4x4 · 9d29d762
      Jian Zhou authored
      Relocate h_predictor_4x4 from SSSE3 to SSE2 with XMM registers.
      Speed up by ~25% in ./test_intra_pred_speed.
      
      Change-Id: I64e14c13b482a471449be3559bfb0da45cf88d9d
      9d29d762
  13. 25 Nov, 2015 2 commits
  14. 23 Nov, 2015 1 commit
  15. 20 Nov, 2015 2 commits
    • James Zern's avatar
      fix vp9_satd_sse2 · 60760f71
      James Zern authored
      accumulate satd in 32-bits
      + add unit test
      
      Change-Id: I6748183df3662ddb9d635f9641f9586f2fd38ad5
      60760f71
    • James Zern's avatar
      vp9_satd: return an int · 3e0138ed
      James Zern authored
      the final sum may use up to 26 bits
      
      + add a unit test
      + disable the sse2 as the result will rollover; this will be fixed in a
      future commit
      
      Change-Id: I2a49811dfaa06abfd9fa1e1e65ed7cd68e4c97ce
      3e0138ed
  16. 19 Nov, 2015 1 commit
    • Jian Zhou's avatar
      Speed up tm_predictor_4x4 · 79b68626
      Jian Zhou authored
      tm_predictor_4x4 is implemented with SSE2 using XMM registers.
      Speed up by ~25% in ./test_intra_pred_speed.
      
      Change-Id: I25074b78d476a2cb17f81cf654bdfd80df2070e0
      79b68626
  17. 14 Nov, 2015 1 commit
  18. 13 Nov, 2015 2 commits
  19. 10 Nov, 2015 1 commit
  20. 09 Nov, 2015 2 commits
  21. 06 Nov, 2015 3 commits
  22. 05 Nov, 2015 1 commit
  23. 03 Nov, 2015 1 commit
  24. 31 Oct, 2015 1 commit
  25. 30 Oct, 2015 1 commit
  26. 29 Oct, 2015 1 commit