1. 15 Nov, 2012 1 commit
  2. 06 Nov, 2012 1 commit
    • Yaowu Xu's avatar
      silent a lot of MSVC compiler warnings · 8a336b0d
      Yaowu Xu authored
      there are still a couple type of warning left, which are related to
      double constants assigned to float type. As those would be addressed
      by the conversion of transforms into integer version. This commit
      has left those un-dealt with.
      
      Change-Id: I48fd9b489c0c27ad6b543f4177423419f929f2bb
      8a336b0d
  3. 05 Nov, 2012 1 commit
  4. 25 Sep, 2012 1 commit
    • Mike Frysinger's avatar
      check for x32 targets · a75a9cf2
      Mike Frysinger authored
      Add configure detection of the new x32 ABI as well as support in asm.
      
      Change-Id: Ic66a069599adeb81062090e3f11b71ee1fb97cb8
      a75a9cf2
  5. 20 Aug, 2012 1 commit
  6. 14 Aug, 2012 1 commit
  7. 17 Jul, 2012 1 commit
  8. 20 Jun, 2012 2 commits
    • Johann's avatar
      Clean Android build defaults · d6e80deb
      Johann authored
      Disable unit-tests. The logging in GTest would need to be adjusted.
      
      Restructure ARM cpu detection. Flatten if-else logic.
      
      Change #if defined(HAVE_*) to #if HAVE_* because we only need to check
      for features that the library was actually built with. This should have
      been harmless, as disabled feature sets wouldn't have any features to
      call.
      
      Change-Id: Iea21aa42ce5f049c53ca0376d25bcd0f36f38284
      d6e80deb
    • Attila Nagy's avatar
      Enables building examples with Android NDK · 5daaa838
      Attila Nagy authored
      Soft enable runtime cpu detect for armv7-android target, so that it
      can be disabled and remove dependency on 'cpufeatures' lib.
      Change the arm_cpu_caps implementation selection such that 'no rtcd' takes
      precedence over system type.
      
      Switch to use -mtune instead of -mcpu. NDK was complaining about
      -mcpu=cortex-a8 conflicting with -march=armv7-a, not sure why.
      
      Add a linker flag to fix some cortex-a8 bug, as suggested by NDK Dev
      Guide.
      
      Examples:
      Configure for armv7+neon:
      
      ./configure --target=armv7-android-gcc \
                  --sdk-path=/path/to/android/ndk \
                  --disable-runtime-cpu-detect \
                  --enable-realtime-only \
                  --disable-unit-tests
      
      ...armv7 w/o neon:
      
      ./configure --target=armv7-android-gcc \
                  --sdk-path=/path/to/android/ndk \
                  --disable-runtime-cpu-detect \
                  --enable-realtime-only \
                  --disable-neon \
                  --cpu=cortex-a9 \
                  --disable-unit-tests
      
      Change-Id: I37e2c0592745208979deec38f7658378d4bd6cfa
      5daaa838
  9. 18 Jun, 2012 2 commits
  10. 12 Jun, 2012 1 commit
  11. 11 Jun, 2012 1 commit
    • John Koleszar's avatar
      Fix pedantic compiler warnings · 0164a1cc
      John Koleszar authored
      Allows building the library with the gcc -pedantic option, for improved
      portabilty. In particular, this commit removes usage of C99/C++ style
      single-line comments and dynamic struct initializers. This is a
      continuation of the work done in commit 97b766a4, which removed most
      of these warnings for decode only builds.
      
      Change-Id: Id453d9c1d9f44cc0381b10c3869fabb0184d5966
      0164a1cc
  12. 05 Jun, 2012 1 commit
    • Alpha Lam's avatar
      asm_*_offsets to define variables as constants · e343988f
      Alpha Lam authored
      This change is to allow obj_int_extract to extract all integers
      in the data segment. With the const keyword these variables are
      forced into the .rodata segment even for zero variable value.
      
      We had a problem before that zero valueed variables would get
      assigned to BSS segment that fooled obj_int_extract to give
      incorrect values.
      
      Change-Id: Icd94f80a8ab356879894ca508bf132d20b865299
      e343988f
  13. 30 May, 2012 1 commit
    • Alpha Lam's avatar
      Make libvpx Chromium build friendly · fc2fc899
      Alpha Lam authored
      Add PRIVATE macro for adding private_extern directive for yasm
      to hide global symbols. This is only enabled if -DCHROMIUM is used
      with YASM.
      
      Also fixed a small problem with	rtcd_defs.sh to guard TEMPORAL_DENOISING.
      
      Change-Id: I9027fce3ebddcf20078293e4b86b396f21da7857
      fc2fc899
  14. 24 May, 2012 2 commits
    • Alpha Lam's avatar
      asm_*_offsets to define variables as constants · 49f7f05f
      Alpha Lam authored
      This change is to allow obj_int_extract to extract all integers
      in the data segment. With the const keyword these variables are
      forced into the .rodata segment even for zero variable value.
      
      We had a problem before that zero valueed variables would get
      assigned to BSS segment that fooled obj_int_extract to give
      incorrect values.
      
      Change-Id: Icd94f80a8ab356879894ca508bf132d20b865299
      49f7f05f
    • Alpha Lam's avatar
      Make libvpx Chromium build friendly · 0f7e4665
      Alpha Lam authored
      Add PRIVATE macro for adding private_extern directive for yasm
      to hide global symbols. This is only enabled if -DCHROMIUM is used
      with YASM.
      
      Also fixed a small problem with	rtcd_defs.sh to guard TEMPORAL_DENOISING.
      
      Change-Id: I9027fce3ebddcf20078293e4b86b396f21da7857
      0f7e4665
  15. 02 May, 2012 1 commit
    • Timothy B. Terriberry's avatar
      Add support for native Solaris compiler on x86. · 8b1a14d1
      Timothy B. Terriberry authored
      Original patch by Ginn Chen <ginn.chen@oracle.com> against libvpx
       v0.9.0.
      I've forward-ported it to the current version (which mostly
       involved removing hunks that were no longer relevant), since I've
       given up on getting Ginn to submit this upstream himself.
      
      Change-Id: I403c757c831c78d820ebcfe417e717b470a1d022
      8b1a14d1
  16. 15 Mar, 2012 1 commit
    • Yaowu Xu's avatar
      WebM Experimental Codec Branch Snapshot · 6035da54
      Yaowu Xu authored
      This is a code snapshot of experimental work currently ongoing for a
      next-generation codec.
      
      The codebase has been cut down considerably from the libvpx baseline.
      For example, we are currently only supporting VBR 2-pass rate control
      and have removed most of the code relating to coding speed, threading,
      error resilience, partitions and various other features.  This is in
      part to make the codebase easier to work on and experiment with, but
      also because we want to have an open discussion about how the bitstream
      will be structured and partitioned and not have that conversation
      constrained by past work.
      
      Our basic working pattern has been to initially encapsulate experiments
      using configure options linked to #IF CONFIG_XXX statements in the
      code. Once experiments have matured and we are reasonably happy that
      they give benefit and can be merged without breaking other experiments,
      we remove the conditional compile statements and merge them in.
      
      Current changes include:
      * Temporal coding experiment for segments (though still only 4 max, it
        will likely be increased).
      * Segment feature experiment - to allow various bits of information to
        be coded at the segment level. Features tested so far include mode
        and reference frame information, limiting end of block offset and
        transform size, alongside Q and loop filter parameters, but this set
        is very fluid.
      * Support for 8x8 transform - 8x8 dct with 2nd order 2x2 haar is used
        in MBs using 16x16 prediction modes within inter frames.
      * Compound prediction (combination of signals from existing predictors
        to create a new predictor).
      * 8 tap interpolation filters and 1/8th pel motion vectors.
      * Loop filter modifications.
      * Various entropy modifications and changes to how entropy contexts and
        updates are handled.
      * Extended quantizer range matched to transform precision improvements.
      
      There are also ongoing further experiments that we hope to merge in the
      near future: For example, coding of motion and other aspects of the
      prediction signal to better support larger image formats, use of larger
      block sizes (e.g. 32x32 and up) and lossless non-transform based coding
      options (especially for key frames). It is our hope that we will be
      able to make regular updates and we will warmly welcome community
      contributions.
      
      Please be warned that, at this stage, the codebase is currently slower
      than VP8 stable branch as most new code has not been optimized, and
      even the 'C' has been deliberately written to be simple and obvious,
      not fast.
      
      The following graphs have the initial test results, numbers in the
      tables measure the compression improvement in terms of percentage. The
      build has  the following optional experiments configured:
      --enable-experimental --enable-enhanced_interp --enable-uvintra
      --enable-high_precision_mv --enable-sixteenth_subpel_uv
      
      CIF Size clips:
      http://getwebm.org/tmp/cif/
      HD size clips:
      http://getwebm.org/tmp/hd/
      (stable_20120309 represents encoding results of WebM master branch
      build as of commit#7a159071)
      
      They were encoded using the following encode parameters:
      --good --cpu-used=0 -t 0 --lag-in-frames=25 --min-q=0 --max-q=63
      --end-usage=0 --auto-alt-ref=1 -p 2 --pass=2 --kf-max-dist=9999
      --kf-min-dist=0 --drop-frame=0 --static-thresh=0 --bias-pct=50
      --minsection-pct=0 --maxsection-pct=800 --sharpness=0
      --arnr-maxframes=7 --arnr-strength=3(for HD,6 for CIF)
      --arnr-type=3
      
      Change-Id: I5c62ed09cfff5815a2bb34e7820d6a810c23183c
      6035da54
  17. 01 Mar, 2012 1 commit
  18. 08 Feb, 2012 1 commit
  19. 20 Jan, 2012 1 commit
    • Fritz Koenig's avatar
      Disconnect ARM tgt_isa from dsp extensions · 89210284
      Fritz Koenig authored
      A processor with ARMv7 instructions does not
      necessarily have NEON dsp extensions.  This CL
      has the added side effect of allowing the ability
      to enable/disable the dsp extensions cleanly.
      
      Change-Id: Ie1e879b8fe131885bc3d4138a0acc9ffe73a36df
      89210284
  20. 18 Jan, 2012 1 commit
    • Fritz Koenig's avatar
      Add makefile for building libvpx for Android. · d8305731
      Fritz Koenig authored
      Android.mk file for using the Android NDK build
      system to compile. Adds option for SDK path to
      use the compiler that comes with android for testing
      compiler compliance.
      
      Change-Id: I5fd17cb76e3ed631758d3f392e62ae1a050d0d10
      d8305731
  21. 06 Jan, 2012 1 commit
  22. 22 Sep, 2011 1 commit
  23. 30 Jun, 2011 1 commit
  24. 08 Jun, 2011 1 commit
    • Johann's avatar
      use GCC inline magic · 79327be6
      Johann authored
      Better fix for #326. ICC happens to support the inline magic
      
      Change-Id: Ic367eea608c88d89475cb7b05d73500d2a1bc42b
      79327be6
  25. 19 Apr, 2011 1 commit
    • Johann's avatar
      modify SAVE_XMM for potential 64bit use · 4a2b684e
      Johann authored
      the win64 abi requires saving and restoring xmm6:xmm15. currently
      SAVE_XMM and RESTORE XMM only allow for saving xmm6:xmm7. allow
      specifying the highest register used and if the stack is unaligned.
      
      Change-Id: Ica5699622ffe3346d3a486f48eef0206c51cf867
      4a2b684e
  26. 18 Apr, 2011 1 commit
    • Johann's avatar
      Add save/restore xmm registers in x86 assembly code · c7cfde42
      Johann authored
      Went through the code and fixed it. Verified on Windows.
      
      Where possible, remove dependencies on xmm[67]
      
      Current code relies on pushing rbp to the stack to get 16 byte
      alignment. This broke when rbp wasn't pushed
      (vp8/encoder/x86/sad_sse3.asm). Work around this by using unaligned
      memory accesses. Revisit this and the offsets in
      vp8/encoder/x86/sad_sse3.asm in another change to SAVE_XMM.
      
      Change-Id: I5f940994d3ebfd977c3d68446cef20fd78b07877
      c7cfde42
  27. 12 Mar, 2011 1 commit
    • Rafael Ávila de Espíndola's avatar
      Fix build with xcode4 and simplify GLOBAL. · 52f6e28e
      Rafael Ávila de Espíndola authored
      Without this change I get link errors in firefox's libxul. It looks
      like the linker expect a particular pattern for getting the GOT. This
      patch changes webm to use the same pattern used by the compiler.
      
      Change-Id: Iea8c2e134ad45c1dc7d221ff885a8429bfa4e057
      52f6e28e
  28. 04 Mar, 2011 1 commit
  29. 17 Feb, 2011 1 commit
    • James Zern's avatar
      documentation: minor cosmetics · f42d52e6
      James Zern authored
      - correct spelling
      - remove explicit file name w/\file (unnecessary when contained in the
        same file and prone to desync)
      
      Change-Id: I68a3960ac5ab84d0f2e5c9b2e29799f26dfccf23
      f42d52e6
  30. 28 Jan, 2011 1 commit
    • Tero Rintaluoma's avatar
      Adds "armvX-none-rvct" targets · 11a222f5
      Tero Rintaluoma authored
      Adds following targets to configure script to support RVCT compilation
      without operating system support (for Profiler or bare metal images).
       - armv5te-none-rvct
       - armv6-none-rvct
       - armv7-none-rvct
      
      To strip OS specific parts from the code "os_support"-config was added
      to script and CONFIG_OS_SUPPORT flag is used in the code to exclude OS
      specific parts such as OS specific includes and function calls for
      timers and threads etc. This was done to enable RVCT compilation for
      profiling purposes or running the image on bare metal target with
      Lauterbach.
      
      Removed separate AREA directives for READONLY data in armv6 and neon
      assembly files to fix the RVCT compilation. Otherwise
      "ldr <reg>, =label" syntax would have been needed to prevent linker
      errors. This syntax is not supported by older gnu assemblers.
      
      Change-Id: I14f4c68529e8c27397502fbc3010a54e505ddb43
      11a222f5
  31. 27 Oct, 2010 1 commit
    • Yunqing Wang's avatar
      Full search SAD function optimization in SSE4.1 · 71ecb5d7
      Yunqing Wang authored
      Use mpsadbw, and calculate 8 sad at once. Function list:
      vp8_sad16x16x8_sse4
      vp8_sad16x8x8_sse4
      vp8_sad8x16x8_sse4
      vp8_sad8x8x8_sse4
      vp8_sad4x4x8_sse4
      
      (test clip: tulip)
      For best quality mode, this gave encoder a 5% performance boost.
      For good quality mode with speed=1, this gave encoder a 3%
      performance boost.
      
      Change-Id: I083b5a39d39144f88dcbccbef95da6498e490134
      71ecb5d7
  32. 25 Oct, 2010 1 commit
    • Timothy B. Terriberry's avatar
      Add runtime CPU detection support for ARM. · b71962fd
      Timothy B. Terriberry authored
      The primary goal is to allow a binary to be built which supports
       NEON, but can fall back to non-NEON routines, since some Android
       devices do not have NEON, even if they are otherwise ARMv7 (e.g.,
       Tegra).
      The configure-generated flags HAVE_ARMV7, etc., are used to decide
       which versions of each function to build, and when
       CONFIG_RUNTIME_CPU_DETECT is enabled, the correct version is chosen
       at run time.
      In order for this to work, the CFLAGS must be set to something
       appropriate (e.g., without -mfpu=neon for ARMv7, and with
       appropriate -march and -mcpu for even earlier configurations), or
       the native C code will not be able to run.
      The ASFLAGS must remain set for the most advanced instruction set
       required at build time, since the ARM assembler will refuse to emit
       them otherwise.
      I have not attempted to make any changes to configure to do this
       automatically.
      Doing so will probably require the addition of new configure options.
      
      Many of the hooks for RTCD on ARM were already there, but a lot of
       the code had bit-rotted, and a good deal of the ARM-specific code
       is not integrated into the RTCD structs at all.
      I did not try to resolve the latter, merely to add the minimal amount
       of protection around them to allow RTCD to work.
      Those functions that were called based on an ifdef at the calling
       site were expanded to check the RTCD flags at that site, but they
       should be added to an RTCD struct somewhere in the future.
      The functions invoked with global function pointers still are, but
       these should be moved into an RTCD struct for thread safety (I
       believe every platform currently supported has atomic pointer
       stores, but this is not guaranteed).
      
      The encoder's boolhuff functions did not even have _c and armv7
       suffixes, and the correct version was resolved at link time.
      The token packing functions did have appropriate suffixes, but the
       version was selected with a define, with no associated RTCD struct.
      However, for both of these, the only armv7 instruction they actually
       used was rbit, and this was completely superfluous, so I reworked
       them to avoid it.
      The only non-ARMv4 instruction remaining in them is clz, which is
       ARMv5 (not even ARMv5TE is required).
      Considering that there are no ARM-specific configs which are not at
       least ARMv5TE, I did not try to detect these at runtime, and simply
       enable them for ARMv5 and above.
      
      Finally, the NEON register saving code was completely non-reentrant,
       since it saved the registers to a global, static variable.
      I moved the storage for this onto the stack.
      A single binary built with this code was tested on an ARM11 (ARMv6)
       and a Cortex A8 (ARMv7 w/NEON), for both the encoder and decoder,
       and produced identical output, while using the correct accelerated
       functions on each.
      I did not test on any earlier processors.
      
      Change-Id: I45cbd63a614f4554c3b325c45d46c0806f009eaa
      b71962fd
  33. 13 Oct, 2010 1 commit
  34. 12 Oct, 2010 1 commit
  35. 04 Oct, 2010 3 commits
    • Jan Kratochvil's avatar
      nasm: avoid relative include paths · fc2b06c6
      Jan Kratochvil authored
      nasm does not automatically assume the source's directory also for its
      include files.
      
      Provide nasm compatibility.  No binary change by this patch with yasm on
      {x86_64,i686}-fedora13-linux-gnu.  Few longer opcodes with nasm on
      {x86_64,i686}-fedora13-linux-gnu have been checked as safe.
      
      Change-Id:	I386efa0cca5d401193416c11bd7363a283541645
      fc2b06c6
    • Jan Kratochvil's avatar
      nasm: address labels 'rel label' vice 'wrt rip' · 5cdc3a4c
      Jan Kratochvil authored
      nasm does not support `label wrt rip', it requires `rel label'. It is
      still fully compatible with yasm.
      
      Provide nasm compatibility. No binary change by this patch with yasm on
      {x86_64,i686}-fedora13-linux-gnu. Few longer opcodes with nasm on
      {x86_64,i686}-fedora13-linux-gnu have been checked as safe.
      
      Change-Id: I488773a4e930a56e43b0cc72d867ee5291215f50
      5cdc3a4c
    • Jan Kratochvil's avatar
      nasm: match instruction length (movd/movq) to parameters · e114f699
      Jan Kratochvil authored
      nasm requires the instruction length (movd/movq) to match to its
      parameters. I find it more clear to really use 64bit instructions when
      we use 64bit registers in the assembly.
      
      Provide nasm compatibility. No binary change by this patch with yasm on
      {x86_64,i686}-fedora13-linux-gnu. Few longer opcodes with nasm on
      {x86_64,i686}-fedora13-linux-gnu have been checked as safe.
      
      Change-Id: Id9b1a5cdfb1bc05697e523c317a296df43d42a91
      e114f699