dboolhuff.c(50) : warning C4267: 'initializing' : conversion from
'size_t' to 'int'

Change-Id: I6b85759efb2fa19f362f406623d8a7583a55c036

This allows code calling the library can choose an arbitrary
encryption algorithm.

Decoder control parameter VP8_SET_DECRYPT_KEY is renamed to
VP8D_SET_DECRYPTOR, and now takes an small config struct instead
of just a byte array.

Change-Id: I0462b3388d8d45057e4f79a6b6777fe713dc546e

Change-Id: If74bc6110016bc75ea3883ab136fbbac88f6a913

to work like vpxenc.  This is required for the frame-based
multithreading.


Change-Id: I338ae9c7d52b0541f3536cc033d6b89f00866e74

The new neighorbhood adapts to the shape and size of the block type
cif +.16%
stdhd +.13%

Change-Id: I978db58278e9ae3fbd6726ef831bdfc5f5f37d02

If the codec was configured with --enable-internal-stats,
a seg fault would occur.  This patch fixes the problem.

Change-Id: Id10a577973d185e93037c59e5b36bebdded327da

Condition the existing zbin boost logic for gf/altf mode to temporal layers==1,
since gf/altf reference frames are used in temporal layers as reference frames.

Change-Id: I618bb20730e5f193e078215d06f54997c363dd7b

datatype is optional for the instruction but clang refuses it.
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0489c/CIHIJIHC.html

It is still required when using an immediate.
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0489c/CIHGGEEB.html

Change-Id: I0fae956c8c0fa3f97578ce80abea247f7fc88705

Previously, the microsoft arm assembler errored out, saying that
bilinear_taps_coeff was an undefined symbol.

Change-Id: Ib938f0b454c41ccbd801e70a7c9acc0fa04e3c55

The microsoft assembler can't handle the second register being
implicit.

Change-Id: Ia831953a78a25fd6b2082474f05fdb78d96cdf78

Use a separate counter for resetting the pattern upon
a change in temporal layers, and set/initialize the
layer context parameters for the new temporal layer state.

Also moved the setting of layer configuation in init_config()
to a separate function.

Change-Id: Ic7fc023a1e5490020509e107004645098f4c00f0

Change-Id: Iee9894615265d42aa23c43a4183924953aedb0c6

The only reason for the _intrinsics part of the file name was for the
interim period where only one of the functions was redone and the base
file name was the same.

Change-Id: I7851154f1633d48821bee885b1cadb2148e65a23

The file uses functions defined in vp8_rtcd.h but did not include the
header.

Change-Id: I110196ddc9181e533be1fe656e21c1791cabe226

This is work-in-progress, it implements multiple ARF
encoding behind an experimental flag.

It adds the ability to insert multiple ARF frames into a
single ARF group. This patch implements the reordering
of the coded frames, and implements a fixed-length coding
pattern. It applies a fixed quantizer strategy based on
where the frame is in the coding sequence.

Further work to modify the rate control strategy is
ongoing and will be submitted via a set of future patches.

In this first step, each ARF group is recursively
bisected and an ARF frame added at that position in the
sequence. The recursion continues until ARF frames are
within MIN_GF_INTERVAL frames.

The code sits behind the "multiple-arf" experimental
flag ("CONFIG_MULTIPLE_ARF"). The experimental flag
"oneshotq" ("CONFIG_ONESHOTQ") also needs to be enabled
for this patch to work correctly.

Change-Id: Ie473b05ebb43ac473c0cfb659b2b8042823085e2

Use local variable for setting the improved prediction mode.
cpi->sf.improved_mv_pred is set/fixed at the frame level
and should not be changed inside pick_inter_mode.

Change-Id: Ie28d9171ac000e631af0e30204970e3d4fff3078

Update to use the new YV12_BUFFER_CONFIG structure.

Change-Id: Ia64757d50cc9019d336fa622e059bf68140d0fa7

Restore ABI compatibility with the master branch.

Change-Id: Ic57e7e1de09ab33bd37990e52a63ba7c8f1432a4

Use unique names and ditch the local label declaration. Visual Studio
does not support it.

https://code.google.com/p/webm/issues/detail?id=561

Change-Id: Ica643cf5abb56ee6156371f5bf73fdeb58014422

This eliminates a tsan warning.

Change-Id: I204d109b12adb4e347762e63d12859244f28d1a9

Change-Id: I0027483e47900de84394de47c3273cc8292e6119

New decoder control paramter VP8_SET_DECRYPT_KEY to set the decryption key.

Change-Id: I6fc1f44d41f74f3b3f702778af1a6f8f5cc9439f

checking CPU capabilities

Reported by Krzysztof Kaspruk.
https://code.google.com/p/webm/issues/detail?id=532

Change-Id: I9efa693b0c33694c871189841b8ac59c1fc554e2

Reported by Krzysztof Kaspruk.
https://code.google.com/p/webm/issues/detail?id=531

Change-Id: Ib5d5878ad07707bd42c2ca833eb021004f537012

and denoising.c
Adding -Wshadow to CFLAGS generated a bunch of warnings.  This patch
removes these warnings.

Change-Id: I434a9f4bfac9ad4ab7d2a67a35ef21e6636280da

Adding -Wshadow to CFLAGS generated a bunch of warnings.  This patch
removes these warnings.

Change-Id: Ib498de4b8652051d257cf86dcb40d2968a5013ae

ratectrl.c and quantize.c

Adding -Wshadow to CFLAGS generated a bunch of warnings.  This patch
removes these warnings.

Change-Id: I8c8faa9fde57c1c49662d332a90bc8d9a0f4a2ce

Adding -Wshadow to CFLAGS generated a bunch of warnings.  This patch
removes these warnings.

Change-Id: I9d52c4a44351607d7d20d52e2a1bffe2a067891a

Adding -Wshadow to CFLAGS generated a bunch of warnings.  This commit
is based on work already done by jzern.

Change-Id: Iefc08a7ab601c4d1b507f039577433bfb1c6cc9d

fixes out of bounds reads on vp8_prob_cost table.
present since:
217591fd Added rate-targeted temporal scalability
v0.9.7-p1-71-g217591fd

Change-Id: I9194b773098a381f1e3f67bd3307f05df27c24fd

Writing all #define guards using the same style. Inlining macro
VP8DX_BOOL_DECODER_FILL into vp8dx_bool_decoder_fill. Removing unnecessary
includes.

Change-Id: I483fa979ab34008bf7835b5f34c6471c44daf956

Change-Id: I5637d491eb6a9b7633f72e03fd9df72131eeb121

Change-Id: I15a6cd014fce8090cdb0441723bd1a90b562579c

make them symmetrical with the generated output and their vp9
counterparts

Change-Id: I72cc97c4d33d713dff620a6d7cc25955266216fc

Remove dependency of this function on asm_offsets. ssse3/sse4 next.

Change quant_shift calculation so it be done using SIMD. Pre-calculate
as much as possible to simplify EOB selection.

Take advantage of qcoeff being zero'd by tying the if statements
together.

Speed parity with previous implementation with gcc x86_64 linux

Change-Id: Ife97556a1eca3a74b09def1a3d04084974dff1fb

gf_group_bits is int64_t remove casts to int.

Change-Id: I3b4225905041fac9af9fdfcbcb6f1c357ea4b593

s/movd/movq/

Change-Id: Id1a56de91551f8dc796f14f1056c565dfc1ba626

Reduce dependency on offsets file by using intrinsics. Disassembly shows
improvements over previous assembly specifically in register management,
preloading, and {pro,epi}log. Speed change is within margin of error.

Change-Id: I8131b4b4d62bc092407fe847bfaa8f2c0e1384ff

Change-Id: I980da3c70f7cee1b723ede0ed2ae527ac7cd6a51

avoids signed integer overflow; matches kf_group_bits

Change-Id: I193145cdc4fa53e70fba0a1731a03eb1a574931d