This is in preparation for the SSE2 version of the high-precision
32x32 forward DCT which will share a lot of code with the existing
low precision version used for rate-distortion search.

Change-Id: I7084b6bdfb480b1fabb8493fb14e3f7fcc7888c0

Support enabling it or disabling it.  Moved read out to configure.sh
so that its done once instead of in make and in config.

Change-Id: I73a9190cf31de9f03e8a577f478fa522f8c01c8b

* changes:
  vp9/decoder: threaded row-based loop filter
  vp9/decoder: add thread worker

Change-Id: I226e5094d216b09dc47fa5511a66e2d314608000

Currently the only threaded option for vp9 decode. Enabled when the
decoder config thread count is > 1.

Change-Id: I082959abac9e31aa4a38ed9fd68b94680e57f4df

vp9/decoder/vp9_thread.[hc]
Original source:
 http://git.chromium.org/webm/libwebp.git
 100644 blob b1615d0fb8d311666b2fa4561076c62d72c2e3ff  src/utils/thread.c
 100644 blob 13a61a4c84194c3374080cbf03d881d3cd6af40d  src/utils/thread.h

Local modifications:
 - s/WebP/VP9/g
 - camelcase functions -> lower with _'s

Change-Id: Ib6932640ee34f8b4782c6fbd15864a59d5d4c5fe

Cons bw/bh parms that should have been const. Additional formatting.

Change-Id: Icd36a5c9dc17dadd7284315ac0d6fef1a565ca16

- new date
- add VP9 to the title
- update list of available targets

Change-Id: I56263336db393020bac5da8e42fbac3a276ffb1f

Chromium does not support 32bit builds for Mac which use x86inc.asm.
Make the files which include it work if 64bit or not PIC enabled
starting with vp9_copy_sse2.asm

Consolidate these targets in vp9_rtcd_defs.sh

Change-Id: If18f0b957a611efd085a3ee7d245cf1eb91e8248

Change-Id: I428c4d42212b757112e3acfe5b81314cfbb5fd6b

This is an attempt at rewriting vp9_find_mv_refs_idx.   I believe that it gains
about 1-2% decode speed

Change-Id: Ia5359c94ce9bb43b32652890e605e9a385485c1b

Consistent names with TX_SIZE, TX_MODE, and TX_MODE.

Change-Id: I79592218bf5a40ace89197a34a06ee7de581ed8d

Change-Id: I94f6b4272b95ac101de6d10f048116ba065788b0

Using it instead of long unclear verbose check
"mbmi->ref_frame[0] != INTRA_FRAME".

Change-Id: I9c7b4b3797942fa962bf3ba7460fff3084beabe9

Change-Id: I8f21c18b29f54b277fb1c167f278f109d9f3b996

Change-Id: Ic878d31df2ce783a2c9a8c4bc9ed301ec8ffe25e

Change-Id: I3fe90eb40088a5b07bdc7d66d93ffe6ef99943d5

Change-Id: Ic07f5f8ffeaedd5b7513b464871f83afc82dcd5c

Change-Id: I0e9329490828684a4fd46f540d89114cc68e8407

Change-Id: I5d6906772e6e6adf68d7f0fd5b8b5207a64a3a37

Change-Id: Ic7cacd02d6dc9243ad8fc85082c5618a9d1e66dc

Loading to single lanes in multiple registers is expensive since
it requires a read and write of each register which saturates
the register file access.  Loading to single registers followed
by a separate transpose reduces this pressure.

Change-Id: I4cc35887ddbca80e5e635b50d2b1d158de9668ee

Change-Id: I13e0880df234f15abc4cc7c57fe84488d5d46a75